Title –Registrations open for FREE hands-on session on VLSI Design using Verilog HDL

Planning to learn new skills this year. Start with this free opportunity of learning VLSI Design using Verilog HDL. This workshop is a great hands-on experience on VLSI concepts from Industry perspective.
Click here to book your slot elearn.maven-silicon.com/free-vlsi-workshop-freshers or call at 98450 16248 | 91486 37555.
Limited seats. Hurry up!!

Workshop Topic: VLSI Design using Verilog HDL

Speaker: Mr. P R Sivakumar (CEO-Maven Silicon with 20+ years of experience in Industry and Academia)

Date: Sun, 20/Jan/2019

Time : 9:00 AM to 1:00 PM

Venue : Maven Silicon

Agenda:
• Overview of VLSI Design
1. IPs, Chips and SoCs
2. SoC Design
3. ASIC Vs FPGA

• RTL Design using Verilog HDL
1. Verilog Language Concepts
2. Verilog language basics and constructs
3. Verilog Abstraction levels
4. Data Types and Operators

• Verilog RTL coding Style - Summary
• Verilog Labs - Hands on Session
• Quiz & Prize distribution

Take away:
• Participation Certificate
• Scholarship Coupon
Venue - # 21/1A, III Floor, Marudhar Avenue, Gottigere,, Uttarahalli Hobli, South Taluk, Bannerghatta Road,, Bengaluru, Karnataka 560076